Wpm P-3.03 Cdsp: an Application-specific Digital Signal Prcbcessor for Third Generation Wireless Communications

This paper presents an application-specific digital signal processor for third generation wireless communications. The processor architecture and instruction set are specially designed for the WCDMA system. These features make the proposed DSP outperform prior arts in terms of several crucial operations of wireless applications. INTRODUCTION Wireless communications related products are more and more popular in these years. In wireless devices, the programmable digital signal processors (DSPs) are widely used to support necessary system flexibility and upgradability. Several programmable DSPs have been presented for wireless communications [ 1-41, These DSPs possess moderate processing capabilities for present second generation wireless systems, such as GSM or IS-95. However, tlie upcoming third generation WCDMA system intends to support real-time multimedia services, and thus demanding for much higher processor performance. The presented application-specific DSP, which is called CDSP, is a more powerful DSP with special instructions and processor architecture for third generation wireless communications. These key features make the CDSP consume much lower processor MIPS and therefore outperform prior arts [ 1-41 in terms of several crucial operations of wireless applications. PROCESSOR ARCHITECTURE Before designing the DSP architecture, the simulation of WCDMA system is firstly considered. After the simulation, several key operations that can be well executed by the DSP are then extracted. The CDSP is specially designed for symbol-rate I/Q channel data processing, and the block diagram of it is shown in Fig. 1. Detailed design issues are discussed in the following subsections. A . Memory Architecture and Pipeline Stages Modified Harvard architecture including one program memory and two two-port data memories is used in CDSP. In single clock cycle, one instruction fetch from program memory, two operand reads from two two-port data memories, and two data writes back to two data memories can be performed simultaneously. There are Five pipeline stages in CDSP: instruction fetch, instruction decode, operand read, execution, and write back. B. Data Path with SubWord Parallel (SWP) CDSP has four separate data path units: ALU (Arithmetic Logic Unit), MAC (Multiply Accumulate), CMP (Comparator), and SFT (Barrel Shifter). The inputs for ALU, SFT, CMP, and accumulator of MAC are 40-bit wide, and inputs for multipliers of MAC are 16-bit wide. The outputs of data path units can be stored into one of the two 40-bit accumulators (DO or D1) or two data memories. All the executions of the four data path units are completed in single cycle. According to our simulation of WCDMA system, 6-bit word length is enough for symbol-rate data. Therefore, a normal 16-bit DSP data path can be divided further into two 8-bit data for I channel and Q channel respectively. By this SWP architecture caf data path, the symbol rate I/Q channel data processing can be efficiently accelerated. Fig.2 shows the SWP architccture of the MAC. 200 0-7803-6622-0101 $10.00